Avionics FPGA Design and Verification Chief Principal Engineer

Company: BOEING
Location: Tempe
Posted on: September 2, 2024

Job Description:

Job DescriptionAt Boeing, we innovate and collaborate to make the world a better place. From the seabed to outer space, you can contribute to work that matters with a company where diversity, equity and inclusion are shared values. We're committed to fostering an environment for every teammate that's welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.Boeing is currently looking for an Avionics FPGA Design and Verification Chief Engineer at the Principal level to join our team in Hazelwood MO, Plano TX, or Mesa, AZ.The successful candidate will be responsible for leading the technical development of a distributed group of engineers focused on FPGA Design, Verification, and Certification for Boeing AvionX products.This position involves technical leadership for a team that develops FPGA solutions for Vehicle Management Systems (VMS), Guidance and Control Units, Computing and Network Infrastructure, and Electrical Power Systems products. - These products are used in many Boeing products such as F-15 Fighter, T-7A Trainer, MQ-25 Autonomous Refueler, Weapons Programs, Commercial Aircraft, and many more.Position Responsibilities:

• Lead FPGA designs, including multi-FPGA programs and teams with design and verification engineers, and manage team execution to meet program milestones
• Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs
• Explore trade-space of potential FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance
• Implement FPGA with latest design practices and tools from block-level microarchitecture and through HDL coding
• Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensurethe design is completed on schedule
• Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation
• Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards
• Drive FPGA-based prototyping and validation depending on program and system requirements and complexity
• Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed
• Train and mentor less senior engineers across the department and help build effective project teamsThis position is expected to be 100% onsite. - The selected candidate will be required to work onsite at one of the listed location options. -This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret clearance post-Start is required. Basic Qualifications (Required Skills/Experience):
  • Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science
  • 10 or more years of professional experience with Hardware-based integration and test of ASIC/FPGA designs
  • 10 or more years of educational and/or work experience working with digital ASIC/FPGA design and verificationPreferred Qualifications (Desired Skills/Experience):
    • Experience with hardware emulators
    • Experience leading FPGA design and/or verification teams, including tracking and reporting progress to stakeholders
    • Leading FPGA design and/or verification teams, including tracking and reporting progress to stakeholders
    • Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
    • Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
    • Ability to create test plans and self-checking and reusable testbenches from scratch
    • Experience developing Functional Coverage Models and Closing Code Coverage
    • Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
    • Proficient in scripting languages: Make, Perl, Python, etc.
    • Revision Control Systems: svn, cvs, git
    • Proficient in Linux Environments
    • Familiarity with space-based design techniques and radiation mitigation
    • Experience with MIL-STD-882E
    • Experience with DO-254Typical Education/Experience: -Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.Relocation: This position offers relocation based on candidate eligibility. -Drug Free Workplace:Boeing -is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.Shift Work Statement: This position is for 1st shift.At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. - Elements of the Total Rewards package include competitive base pay and variable compensation opportunities. -The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work. -The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.Pay is based upon candidate experience and qualifications, as well as market and business considerations. -Summary pay range: $177,650 - $257,600Applications for this position will be accepted until September 2, 2024.Export Control Requirements: U.S. Government Export Control Status: This position must meet export control compliance requirements. To meet export control compliance requirements, a "U.S. Person" as defined by 22 C.F.R. -120.15 is required. "U.S. Person" includes U.S. Citizen, lawful permanent resident, refugee, or asylee.Export Control Details: US based job, US Person requiredEqual Opportunity Employer:Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.

Keywords: BOEING, Tempe , Avionics FPGA Design and Verification Chief Principal Engineer, Other , Tempe, Arizona