Business Unit: IoT and Infrastructure Business Unit
Job Type: Permanent
Description: Renesas Electronics Americas (REA) is a dynamic,
multi-cultural tech company where employees can learn, mentor and
thrive. REA brings together the strong financial foundation of a
multi-billion dollar global operation and the flexibility and
velocity of a smaller organization. We are developing technologies
for the latest advances in mobile computing, secured connected
devices, autonomous driving, smart homes and factories and more.
Our solutions are at the heart of products developed by the major
innovators around the world. Join us and be part of what’s next in
Analog / Mixed-Signal IC design engineering position that will
provide key contributions to state-of-the-art circuits for use in
high performance networking and communications products.
Involvement in product definition, design, layout, lab
verification, and release to production.
Candidate’s specialized knowledge: The candidate possesses a
deep understanding of analog PLL circuit design techniques.
Utilizes an analytic approach to analog IC design. Understands the
impact of the style of the cell and inductor layout on the
performance of the design, the importance of the efficient usage of
the tools and methodologies to design and satisfy the specification
for customer. Specifically, he understands all the techniques and
tradeoffs required when designing a PLL part comprising of a highly
programmable, low jitter, and self-calibrated analog LC VCO and
techniques to keep phase noise to a minimum. In addition, the
candidate has developed new techniques to reduce power & retain
competitive performance for new PLLs.
A PhD or a MSEE with 8 years professional IC design experience
with strong emphasis on very high performance PLL design.
A solid track record in CMOS and/or BiCMOS IC design is
Strong experience in designing low phase noise PLLs,
fractional-N synthesizers, LC-VCOs, and state machines.
Related experience in digital PLLs, crystal oscillators, VCXOs,
on-chip regulators, DACs and ADCs is desirable.
An understanding of transistor modeling and circuit noise theory
Digital design skills are helpful but not required.
Great attitude, self-motivation and excellent team work is a
Minimum specialized knowledge necessary to perform the job:
process technology and physics related to sub-micron CMOS and
BiCMOS silicon technologies;
design & layout of low phase noise integer PLLs, fractional-N
synthesizers, LC-VCOs, and state machines;
transistor modeling, circuit noise theory, phase noise concepts,
and sigma delta concepts;
simulation tools (e.g., Cadence);
simulation models, design rules, verification procedures
(DRC/LVS/ERC), and transistor-level simulations.
Equal Opportunity Employer: Disability/Veteran