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Mid to Sr. FPGA Design & Verification Engineer

Company: Kforce Technology
Location: Tempe
Posted on: September 14, 2023

Job Description:

Kforce's client, a growing and established company is seeking a Mid to Sr. FPGA Design & Verification Engineer in Tempe, AZ.

Summary:
We are working directly with the Hiring Manager on this search assignment. The company offers a competitive compensation package including base salary, annual bonus, 401K matching, PTO, Etc. This position is partial remote.

Responsibilities:

  • Architect, design, and verify FPGA designs; This position offers an opportunity to collaborate closely with other FPGA design and verification engineers in a team effort focusing primarily on space solid-state data recorders (SSDRs) and System in Package (SiP) firmware solutions
  • Responsible for spanning all phases of the FPGA development life cycle, including requirements analysis, design and code, verification, integration, and documentation
  • Support research, development, integration, and verification of modular, firmware solutions for complex microelectronic components across multiple FPGA vendors
  • Develop and optimize test firmware for design verification and production verification of devices to improve coverage, performance, etc.
  • Create module-level verification using HDL simulations
  • Execute verification simulations, analyze, and document results
  • Support development of firmware requirements and specifications
  • Support design team to reproduce, troubleshoot, and resolve customer issues
  • Support design team with bring-up and test of software products
  • May provide work leadership and/or training to lower-level professionals and technical staff
  • Willing to help the team in areas outside of specific technical discipline

Keywords: Kforce Technology, Tempe , Mid to Sr. FPGA Design & Verification Engineer, Engineering , Tempe, Arizona

Click here to apply!

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